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Xilinx LogiCORE IP User Manual

Xilinx LogiCORE IP User Manual

Xilinx logicore ip video scaler v4.0 user guide
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LogiCORE™ IP
Video Scaler v4.0
User Guide
UG805 March 1, 2011

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  • Page 1 LogiCORE™ IP Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 2: Revision History

    © Copyright 2009-2011 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.Xilinx, Inc.

  • Page 3: Table Of Contents

    ..........28 UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...
  • Page 4 ..............71 UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...
  • Page 5 ............96 UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...
  • Page 6 Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 7: Schedule Of Figures

    Figure 8-2: Coefficient Loading Mechanism, Including External FIFO ....43 Figure 8-3: Coefficient Loading Procedure – One Phase (8-tap filter shown) ..44 UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...
  • Page 8 Figure C-1: Simplified System Diagram ......... 94 UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...

  • Page 9: Schedule Of Tables

    Table 9-1: Target Maximum Clock Frequencies ........61 Table 9-2: Throughput Calculations for Different Chroma Formats ....63 UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...
  • Page 10 Table B-28: Down Sample Register Settings ........91 Appendix C: System Level Design UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide...

  • Page 11: Preface: About This Guide

    The LogiCORE™ IP Video Scaler v4.0 User Guide provides information about generating the Video Scaler core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. Guide Contents This manual contains the following chapters: •...

  • Page 12: Additional Resources

    To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support/mysupport.htm. Conventions This document uses the following conventions. An example illustrates each convention.

  • Page 13: Online Document

    Cross-reference link to a location Blue text in the current document Additional Resources, page 12,” for details. Go to www.xilinx.com for the Blue, underlined text Hyperlink to a website (URL) latest speed files. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 14 Preface: About This Guide www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 15: Chapter 1: Introduction

    Xilinx. See www.xilinx.com/products/ipcenter/EF-DI-VID-SCALER.htm. About the Core The Video Scaler core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see the...

  • Page 16: Providing Feedback

    Chapter 1: Introduction Providing Feedback Xilinx welcomes comments and suggestions about the Video Scaler core and the documentation supplied with the core. Core For comments or suggestions about the Video Scaler core, submit a WebCase from www.xilinx.com/support. Be sure to include the following information: •...
  • Page 17 Coefficient Set A group of four coefficient banks (VY, VC, HY, HC). One full set should be written into the scaler before use. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 18 Chapter 1: Introduction www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 19: Chapter 2: Overview

    Y lines. Within predefined limits, the Xilinx Video Scaler supports the modification of the X input parameters during run-time on a frame basis. Furthermore, you may also dynamically crop selected subject area from the input image prior to scaling that area. This dynamic combination lends itself well to applications that require shrink and zoom functionality.
  • Page 20 Chapter 2: Overview www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 21: Chapter 3: Implementation

    This section elaborates on the internal structure in the core, and describes interfacing. Basic Architecture The Xilinx Video Scaler LogiCORE™ IP converts a specified rectangular area of an input digital video image from the original sampling grid to a desired target sampling grid (Figure 3-1).

  • Page 22: I/O Buffering, Clock Domains

    Figure 3-2. The control state- machines monitor the I/O line buffers. They also monitor the current input and output line numbers. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 23: Data Source: Live Video

    (> 3) clock cycles later to indicate availability of the other half of the double buffer. The number of clock cycles is dependent on the current conversion. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 24 Since it is impossible to hold off a live video feed, the data must be fed (directly or indirectly) from a frame buffer, and the appropriate external control provided (Memory Mode). www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 25: Hblank_In Input

    During vblank_in, hblank_in must continue to be active (as per most video formats). Frame_rst is generated when the number of hblank_in pulses equals Frame Reset Line Number Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 26: Active_Video_In Input

    This parameter is provided as an input to the scaler by the user. You may choose to use the inverse of hblank_in to create the active_video_in signal. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 27: Data Source: Memory

    0. Cropping can be achieved using memory offsets. The first pixel and line provided to the scaler will always be included in the horizontal and vertical apertures. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 28: Output Data And Timing Signals

    Figure 4-6. X-Ref Target - Figure 4-6 video_data_out (7:0) (Luma) Line1 Line2 Line3 Line4 video_data_out (15:8) (Chroma) Valid Valid chroma_out UG678_5-5_081809 Figure 4-6: Scaler 4:2:0 Output Validation (8-bits) www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 29: Chapter 5: Scaler Architectures

    The input line buffer also serves as the “most recent” vertical tap (that is, the lowest in the image) in the vertical filter. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 30: 4:2:0 Special Requirements

    1* DataWidth 1* DataWidth Scaler Engine  Output Line  Buffer  (Ch3) 1*DataWidth  Buffer (Ch3)  1* DataWidth Figure 5-3: Internal Data Path Bitwidths for Triple-Engine RGB/4:4:4 Architecture For this case, all three channels are processed in synchrony. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 31: Gui Operation

    := max(MaxVSizeIn, MaxVSizeOut); max_frame_cycles := max_pixels * max_lines * OverHeadMultiplier; MaxFrameRateOneComponent := (TgtFMax * 1000000)/max_frame_cycles; if (TgtFrameRate <= MaxFrameRateOneComponent/2) then Use Single engine else Use Dual engine end if; Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 32 X-Ref Target - Figure 5-5 Figure 5-5: CORE Generator GUI Information Tab www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 33: Chapter 6: Control Interface

    They should be supplied as integers, and can typically be calculated as follows:  aperture pixel aperture start pixel  round  output size  aperture line aperture start line  round  output size Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 34 • bit 1 enables values on the other register inputs to become internally active on a vblank_in basis. A value of 0 prevents the active internal values from being changed. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 35: Constant (Fixed) Mode

    General Purpose Processor (GPP) Interface This interface type exposes all control ports to the user. You are responsible for driving these ports. Xilinx recommends that GPP mode be used only by experienced scaler users. Figure 6-1 indicates how the EDK pCore is effectively a wrapper around the GPP mode core.

  • Page 36: Edk Pcore Interface

    ScalerExternalSM.vhd syncgen_core.vhd user_logic.vhd v_scaler_v4_0.vhd xscaler.vhd YCCheckSum.vhd For use in an EDK project: Copy the /drivers/scaler_v3_01_a sub-directory from the CORE Generator database to the /drivers directory in your EDK project repository. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 37: Parameter Modification In Core Generator

    Two frames after CoefMemRdEn is written high, this signal is driven high again. In GPP mode, all seven interrupts are active. In Constant mode, only intr_input_error, intr_output_error and intr_output_frame_done are active. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 38 Figure 6-1. It shows the intended usage of interrupts in an EDK-based system. It also shows how the Xilinx Interrupt Controller is used internally to the pCore along with the scaler in GPP mode. X-Ref Target - Figure 6-1 Figure 6-1: Typical EDK-based System Showing Interrupt Structure www.xilinx.com...

  • Page 39: Input Aperture Definition

    Figure 7-1. The falling edge of vblank_in occurs while hblank_in is still high. X-Ref Target - Figure 7-1 Figure 7-1: Hblank_in at Falling Edge of VBlank_in Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 40: Cropping

    Figure 7-3: Cropping from the Input Image When using “Memory” mode, cropping must be achieved by selecting the appropriate rectangular area from memory. aperture_start_pixel and aperture_start_line must be set to zero. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 41: Chapter 8: Coefficients

    This method simplifies internal addressing. When the chroma format is set to 4:4:4., one set of coefficients will be shared between all three channels (i.e., R, G, and B will be scaled identically). Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 42: Coefficient Interface

    The word format is shown in Figure 8-1. X-Ref Target - Figure 8-1 Valid - Coefficient n Valid - Coefficient n+1 16-bit Coefficients UG_28_031909 Figure 8-1: Coefficient Write-Format on coef_data_in(31:0) www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 43 8-3. An internal state-machine detects the 3rd ‘clk’ period when coef_wr_en is stable and high. At this point, the data is registered into the FIFO. Xilinx recommends that the high coef_wr_en pulse be no less than the equivalent of 6 ‘clk’...

  • Page 44: Examples Of Coefficient Set Generation And Loading

    16-bit integers required by the hardware. For this process, coef_width = 16. Note that this is only pseudo code. Generation of actual coefficients is www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 45 (Ph0 T5 << 16) | Ph0 T4 0x00004000 (Ph0 T5 << 16) | Ph0 T4 0x00000000 (Ph0 T7 << 16) | Ph0 T6 0x00000000 (Ph0 T7 << 16) | Ph0 T6 Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 46 (Ph3 T5 << 16) | Ph3 T4 0xF7491457 (Ph3 T5 << 16) | Ph3 T4 0xFBEF058C (Ph3 T7 << 16) | Ph3 T6 0xFBEF058C (Ph3 T7 << 16) | Ph3 T6 www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 47: Example 2: Num_H_Taps = Num_V_Taps = 8; Max_Phases = 5, 6, 7 Or 8; Num_H_Phases = Num_V_Phases = 4

    N/A Dummy coef 0x00000000 N/A Dummy coef 0x00000000 N/A Dummy coef 0x00000000 N/A Dummy coef 0x00000000 N/A Dummy coef 0x00000000 N/A Dummy coef 0x00000000 N/A Dummy coef 0x00000000 N/A Dummy coef Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 48 (Ph3 T5 << 16) | Ph3 T4 0xF7491457 (Ph3 T5 << 16) | Ph3 T4 0xFBEF058C (Ph3 T7 << 16) | Ph3 T6 0xFBEF058C (Ph3 T7 << 16) | Ph3 T6 www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 49: Example 3: Num_H_Taps = 9; Num_V_Taps = 7; Max_Phases = Num_H_Phases = Num_V_Phases = 4

    0x0000 0x0000 0x0000 0xFFB1 0x0123 0x047C 0x10C6 0x3A26 0xF5F0 0x037D 0xFF0A 0x0046 0xFF84 0x01D1 0xF865 0x2490 0x2A42 0xF3D0 0x0490 0xFEB4 0x0060 0xFF9E 0x017E 0xF93F 0x3619 0x14D7 0xF846 0x0312 0xFF1B 0x0043 Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 50 0XFF1B0312 (Ph3 T1 << 16) | Ph3 T6 0XFF1B0312 (Ph3 T1 << 16) | Ph3 T6 0x00000043 (0 << 16) | Ph3 T8 0x00000043 (0 << 16) | Ph3 T8 www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 51 0X01DFF8B1 (Ph3 T1 << 16) | Ph3 T4 0X0000FFA5 (0 << 16) | Ph3 T6 0X0000FFA5 (0 << 16) | Ph3 T6 0x00000000 N/A dummy coef 0x00000000 N/A dummy coef Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 52: Coefficient Preloading Using A .Coe File

    Down-scaling 1080 to 1000 : Use bin 16 • Down-scaling 1080 to 144 : Use bin 4 Unity coefficient in center tap 1920/1280 Example user-specific case for HD down (1080/720) scaling conversion www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 53: Format For .Coe Files

    • Number of coefficient entries in all sets depends upon: • Max_coef_sets • Max_phases • Max_taps (=max(num_h_taps, num_v_taps)) • User setting for "Separate Y/C coefficients" • User setting for “Chroma_format” Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 54 .coe file with the following specification: num_h_taps = num_v_taps = 12; max_phases = 4; max_coef_sets = 1; Separate H/V Coefficients = False; Separate Y/C Coefficients = False; www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 55 0000000010011011, -186, 1111111101000110, -1062, 1111101111001010, 960, 0000001111000000, 6311, 0001100010100111, 7842, 0001111010100010, 3246, 0000110010101110, -538, 1111110111100110, -518, 1111110111111010, 0000000001001000, 0000000001001001, 0000000000110101, 125, 0000000001111101, -366, 1111111010010010, -890, 1111110010000110, 2060, 0000100000001100, 7209, 0001110000101001, Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 56 .coe file with the following specification: num_h_taps = 12, num_v_taps = 12; max_phases = 4; max_coef_sets = 2; Separate H/V Coefficients = True; Separate Y/C Coefficients = True; www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 57 1 (HC) 1 (HC) … … … 1 (HC) 2 (VY) 2 (VY) 162, 2 (VY) … … … … … 2 (VY) 2 (VY) 2 (VY) … … … Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 58 .coe file with the following specification: num_h_taps = 4, num_v_taps = 3; max_phases = 4; max_coef_sets = 1; Separate H/V Coefficients = True; Separate Y/C Coefficients = False; www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 59 Padding value 1 (V) 512, 1 (V) 16068, 1 (V) -197, 1 (V) Padding value 1 (V) 1243, 1 (V) 15539, 1 (V) -398, 1 (V) Padding value 1 (V) 2829, Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 60: Coefficient Readback

    The coefficient will appear at coef_mem_output three clk cycles later. Reading back coefficients does not cause image distortion, and may be executed during normal operation. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 61: Chapter 9: Performance

    It is very important to ensure that the clock rate available supports worst-case conversions. This chapter includes detailed information and examples for worst-case scenarios. Every user of the Xilinx Video Scaler should have a worst-case scenario in mind. The factors that may contribute to this scenario include: •...

  • Page 62: Live Video Mode

    This is required due to filter latency and State-Machine initialization. For all cases in this document, this has been approximated as 50 cycles per component per line. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 63 ProcessingOverheadPerComponent overhead factor must be included in the equation. The number of times this overhead needs to be factored in depends upon the number of components processed by the worst-case engine. CyclesRequiredPerOutputLine=Max(output_h_size,SubjWidth)+Proces singOverheadPerComponent Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 64 (1/1.0) = 0x100000 This case is possible with no input buffer using Spartan-3A DSP because the MinF'clk is less than the core Fmax, as shown in Table 9-1. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 65 Shrink-factor inputs: hsf=220 x (1/1.25) = 0x0CCCCC vsf=220 x (1/1.25) = 0x0CCCCC For a dual-engine implementation, without an input frame buffer, this conversion will work in devices that support this clock-frequency. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 66 MinF'clk' = 67500*2020 = 136.35 MHz Shrink-factor inputs: hsf=220 x (1/0.6667) = 0x180000 vsf=220 x (1/0.6667) = 0x180000 This conversion will work in any of the supported devices and speed grades. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 67: Memory Mode

    This is required mainly due to vertical filter latency. For all cases in this document, this has been generally approximated as 10000 cycles per frame. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 68 CyclesPerOutputFrame = Max [ ((output_h_size*2) + (ProcessingOverheadPerLine*3))*output_v_size, ((input_h_size*2) + (ProcessingOverheadPerLine*3))*input_v_size + FrameProcessingOverhead It is then necessary to decide the minimum 'clk' frequency according to this calculation: MinF'clk' = FFrameIn x CyclesPerOutputFrame www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 69 (1/0.8) = 0x155555 This conversion is allowed in Spartan-3A DSP. Note: Example 9 showed that the same conversion with no frame buffer is not possible in Spartan-3A DSP. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 70 Chapter 9: Performance www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 71: Typical Uses

    = 719 output_h_size = 640 aperture_start_pixel = 0 aperture_end_pixel = 1279 UG_01_031909 Figure A-1: Format Down-scaling. Example 720p to 640x480, HSF = 2 x 1280/640; VSF = 2 x 720/480 Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 72 = 719 output_h_size = 480 aperture_end_pixel = 1279 aperture_start_pixel = 0 UG678_4-6_081809 Figure A-4: Shrink (Down-scaling). Example for Picture-in-Picture (PinP), HSF = 2 x 1280/480; VSF = 2 x 720/270 www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 73 = 720 aperture_start_line aperture_end_line = 269 UG678_4-7_081809 aperture_start_pixel = 0 aperture_end_pixel = 479 Figure A-5: Zoom (Up-scaling) reading from External Memory, HSF = 2 x 480/1280; VSF = 2 x 270/720 Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 74 Appendix A: Use Cases www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 75: Appendix B: Programmer Guide

    Location of first subject pixel in input line, relative to first active pixel in that line 0x0018 aperture_horz aperture_end_pixel: Location of final subject pixel in input line, relative to first active pixel in that line Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 76 Interrupt Status Register; Read to determine the source of the 0x0220 interrupt, write to clear the interrupt Interrupt Enable Register; 0 to mask out an interrupt, 1 to enable 0x0228 an interrupt www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 77 If this bit is '1' then the Coeffs can be written into the core. Coef_write_rdy Check at the beginning of a coeff transfer. Table B-4: status Register 0x0008 status_error Error_Code3 Error_Code2 Error_Code1 Error_Code0 Name Bits Description Error_Code3 31:24 Error codes to be defined Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 78 Name Bits Description Reserved 31:24 Reserved hsf_int 23:20 Horizontal Shrink Factor integer hsf_frac 19:0 Horizontal Shrink Factor fractional Table B-7: vsf Register 0x0014 vert_shrink_factor Reserved vsf_int vsf_frac Name Bits Description www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 79 Location of first line in active video Table B-10: output_size Register 0x0020 output_size Reserved output_v_size Reserved output_h_size Name Bits Description Reserved 31:27 Reserved output_v_size 28:16 Number of lines in output image Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 80 Active horizontal coefficient set Table B-13: start_hpa_y Register 0x002c start_hpa_y Reserved start_hpa_y Name Bits Description Reserved 31:21 Reserved Fractional value used to initialize horizontal accumulator start_hpa_y 20:0 for luma www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 81 Table B-16: start_vpa_c Register 0x0038 start_vpa_c Reserved start_vpa_c Name Bits Description Reserved 31:21 Reserved Fractional value used to initialize vertical accumulator for start_vpa_c 20:0 chroma Table B-17: Coefficient_write_set_address Register 0x003c coef_write_set_addr Reserved coef_wsa Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 82 Bank Name Bits Description Coeff Readback Set 11:8 Coefficient set to be read from the scaler Coefficient bank to be read from scaler: Coeff Readback Bank 00=HY; 01=HC; 10=VY; 11=VC www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 83 Table B-23: Software Reset Register 0x0100 Software_Reset Reserved Name Bits Description Soft Reset to reset the registers and IP core, data Value Soft_Reset_Value 31:0 provided by the EDK create peripheral utility Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 84 Stays low once intr_coef_fifo_rdy a full set has been written into FIFO. Sent high during Vertical blanking. intr_output_frame_ Rising edge sensitive: issued once per complete output done frame. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 85: Filter Coefficient Calculations

    The MATLAB software FIR1 function can be used as a starting point for deriving coefficient values. Xilinx provides a C-Model that generates coefficients. Contact Xilinx support for information on how to obtain this C-Model. Refer to the Video Scaler Product Page information about accessing the C-Model.

  • Page 86: Video Scaler Flow Diagram

    Coef Bank? Set Active Coef Bank Set Load Coef Bank Enable Video Scaler Control Load Coefs Done? Done? Disable Stop Scaler Scaling Control UG678_01_030210 Figure B-0: Video Scaler Flow Chart www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 87: System Timing Diagram

    System Timing Diagram System Timing Diagram Figure B-0: System Timing Diagram Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 88: Proposed Api Function Calls

    #define XScaler_SetHoriAccuLuma(InstancePtr, Fraction) #define XScaler_GetHoriAccuLuma(InstancePtr) #define XScaler_SetVertAccuLuma(InstancePtr, Fraction) #define XScaler_GetVertAccuLuma(InstancePtr) #define XScaler_SetHoriAccuChroma(InstancePtr, Fraction) #define XScaler_GetHoriAccuChroma(InstancePtr) #define XScaler_SetVertAccuChroma(InstancePtr, Fraction) #define XScaler_GetVertAccuChroma(InstancePtr) #define XScaler_SetWriteCoeffBankAddr(InstancePtr, Address) #define XScaler_GetWriteCoeffBankAddr(InstancePtr) #define XScaler_SetCoefValue(InstancePtr, NPlus1, N) #define XScaler_GetCoefValue(InstancePtr) www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 89: L1 Api Function Calls

    4 coeff banks for 200 frames switch bank every 50 frames. #define XScaler_DownSize(InstancePtr, downsize_factor_h, downsize_factor_v, num_of_frames) Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 90: Example Settings

    0x0020 Output_h_size 1280 0x0020 Output_v_size 0x0024 num_h_phases 0x0024 num_v_phases 0x0028 h_coeff_set 0x0028 v_coeff_set 0x002c start_hpa _y 0x0030 start_hpa_c 0x0034 start_vpa_y 0x0038 start_vpa_c 0x003c Coef_set_write_addr Chapter 8, 0x0040 Coef_values Coefficients www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 91: Down Sample By 2 In Horizontal And Vertical

    0x001c aperture_end_line 0x0020 Output_h_size 0x0020 Output_v_size 0x0024 num_h_phases 0x0024 num_v_phases 0x0028 h_coeff_set 0x0028 v_coeff_set 0x002c start_hpa_y 0x0030 start_hpa_c 0x0034 start_vpa_y 0x0038 start_vpa_c 0x003c Coef_set_write_addr Chapter 8, 0x0040 Coef_values Coefficients Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 92 Appendix B: Programmer Guide www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 93: Appendix C: System Level Design

    • The Timebase Controller is a SW-configurable timing detector and generator block, which generates timing signals for distribution around the system. See the Timing Controller Data Sheet for more information. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 94: Control Buses

    VDMA0, in the MHS file text given below, is sourced from an engineering test-pattern generator (not included in the MHS file below). This generates a VDMA write bus that connects directly to the VDMA write port. www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

  • Page 95: Vdma1 Configuration

    This ensures that the rd_almost_empty flag will not be driven low until an entire line of video data is in the FIFO, ready for the scaler to accept. Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...

  • Page 96: Scaler Write-Port

    PARAMETER C_CROP_ENABLE = 1 PARAMETER C_DMA_TYPE = 2 PARAMETER C_BASEADDR = 0xcb480000 PARAMETER C_HIGHADDR = 0xcb48ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE XIL_VFBC = vdma_0_XIL_VFBC BUS_INTERFACE XIL_WD_VDMA = tpg_0_XIL_VDMA_TPG_OUT PORT IP2INTC_Irpt = vdma_0_IP2INTC_Irpt www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 97 PORT clk = vid_in_clkx2 PORT video_in_clk = vid_in_clk PORT video_out_clk = vid_in_clk PORT debug = xscaler_0_LEDsOut PORT IP2INTC_Irpt = scaler_0_IP2INTC_Irpt PORT vsync_i = timebase_1_XSVI_OUT_vsync BEGIN vdma PARAMETER INSTANCE = vdma_2 Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 98 PARAMETER C_ICACHE_LINE_LEN = 8 PARAMETER C_USE_MMU = 3 PARAMETER C_MMU_ZONES = 2 PARAMETER C_PVR = 2 BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DXCL = microblaze_0_DXCL BUS_INTERFACE IXCL = microblaze_0_IXCL www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 99 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = plbv46_axi_bridge_0.M_AXI BUS_INTERFACE S_AXI = axi_interconnect_0 PORT RX = fpga_0_RS232_Uart_1_RX_pin PORT TX = fpga_0_RS232_Uart_1_TX_pin PORT Interrupt = RS232_Uart_1_Interrupt PORT S_AXI_ACLK = clk_100_0000MHzMMCM0 BEGIN mpmc PARAMETER INSTANCE = DDR3_SDRAM Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 100 PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...
  • Page 101 PORT CLKOUT0 = vid_in_clk PORT CLKOUT1 = vid_in_clkx2 PORT RST = dcm_0_rst BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 2.01.a PARAMETER C_BASEADDR = 0x81800000 PARAMETER C_HIGHADDR = 0x8180ffff Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011...
  • Page 102 BUS_INTERFACE M_AXI = axi_interconnect_0 PORT M_AXI_ACLK = clk_100_0000MHzMMCM0 PORT M_AXI_ARESETN = proc_sys_reset_0_Interconnect_aresetn BEGIN axi_interconnect PARAMETER INSTANCE = axi_interconnect_0 PARAMETER HW_VER = 1.02.a PORT INTERCONNECT_ACLK = clk_100_0000MHzMMCM0 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn www.xilinx.com Video Scaler v4.0 User Guide UG805 March 1, 2011...

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